Optoelectronic integrated circuits (OEICs) by definition comprise electronic devices integrated together with active and passive optical devices and enable the concurrent manipulation of both optical and electrical signals. An OEIC designer is able to use the best properties of both optical and electronic devices. Optoelectronic components may be integrated onto a semiconductor wafer either monolithically, where all of the optoelectronic components are fabricated on the wafer, or in hybrid fashion, where some or all of the components are fabricated separately and attached to the wafer.
Efficient coupling and transport of light amongst optoelectronic components integrated onto a semiconductor wafer is a fundamental requirement of OEICs. Such connectivity enables a high degree of functionality to be integrated onto the semiconductor wafer, helping to achieve the primary objectives of OEICs, these being compactness, ease of manufacture, and robustness. One means of accomplishing these objectives is to interconnect distinct optoelectronic components with optical waveguides. An optical waveguide provides a low-loss, confined pathway for the propagating optical signal.
Traditional planar waveguides have been implemented using a structure consisting of a core layer between two cladding layers (see FIG. 1). The index of refraction of the core is larger than the index of the adjacent cladding layers at the optical wavelength of the light propagating within the waveguide. The index of refraction is a property of a material and will vary with the optical wavelength of the light propagating within the material.
For any particular waveguide structure more than one pattern of optical energy distribution across the waveguide may exist. Each pattern defines a mode of the waveguide. A propagating optical signal will have some energy in each allowable mode of the waveguide. However, the lowest order mode will carry the largest percentage of optical energy. The modes that a designed waveguide will sustain are determined by the physical dimensions of the various layers, the properties of the core and cladding layer materials, the difference between the index of refraction of the core and the cladding, and the degree of absorption in the core and cladding layers. A planar waveguide is typically designed such that all the optical energy is confined to the plane of the waveguide by virtue of total internal reflection of the propagating optical signal. However, in the lateral direction the light is free to diffuse.
In a channel waveguide, the light is confined in both the lateral direction and the vertical direction by defining a variation in the index of refraction or the effective index of refraction laterally as well as vertically.
Typically, such optical waveguides have been constructed of group III and group V (referring to the periodic table of the elements) compounds. For example, binary compounds such as GaAs for the cladding and ternary compounds such as InGaAs for the core have been used. These are not easily fabricated on a semiconductor wafer.
A major challenge has been and remains how to integrate OEICs within silicon based VLSI (very large scale integration) integrated circuits which have been well established for many years.
Such VLSI integrated circuits typically comprise both CMOS (complementary metal oxide semiconductor) transistors and bipolar transistors which may be used, for example, in telecommunications applications requiring high speed, high drive, mixed voltage and analog-digital performance.
In contrast to the fabrication of waveguides, VLSI integrated circuits are based on a single semiconductor element, namely silicon. More particularly, bipolar and CMOS devices are constructed by establishing defined regions of N type and P type doped silicon material and physically making electrical contact to those regions as required to supply or extract electronic current or voltage.
Silicon VLSI processing may entail the formation of a device well. The device well does not contribute to the functionality of the device per se, but simply serves to electrically isolate adjacent devices. The device well may be an area of silicon which is surrounded by thick oxide formed using the process of local oxidation of silicon (LOCOS) or by other means including silicon dioxide deposition. Alternatively, a device well may be created by etching deep trenches around an area of silicon.
In addition to doping and oxidation processes, silicon VLSI processing may entail exposure of the wafer to high temperatures and oxidizing ambients. For example, the LOCOS process may require that the wafers be placed in an oxygen environment at temperatures greater than 1000 degrees Celsius. Thus, any additional structural attributes or material characteristics associated with and relied upon by the passive and active optical devices must be able to sustain the conventional steps required in the formation of modern VLSI circuits on a silicon substrate.
A first step in integrating OEICs within silicon VLSI circuits is to establish an optical waveguide structure compatible with the silicon VLSI manufacturing technique.
Proposals in this area have already been made. For example, Namavar and Soref 1! have proposed a planar waveguide based on silicon in which cladding layers are silicon and the core is a silicon germanium alloy (FIG. 2). Additionally, Soref 2! has proposed a channel waveguide in which a silicon germanium alloy is formed on a silicon substrate and a ridge is formed in the silicon germanium layer (FIG. 4).
The existing waveguides do not meet the considerable challenge of optimizing the performance of both CMOS and bipolar devices, concurrent with the optimization of optical waveguides and other optoelectronic components on the same substrate. They do not offer a manufacturable fabrication process for minimum geometry integrated circuits and waveguides which does not inordinately increase the existing VLSI process complexity. Instead, they result in an increase in the number of photolithographic mask levels and process steps, requiring reactive ion etching. Ridges introduce surface topography which is detrimental to photolithographic resolution. In addition, it is not clear that these methods of fabrication produce a VLSI circuit which performs equally well regardless of the presence of the optical waveguides.